1. Field of the Invention
The present invention relates to semiconductor memory circuits and, in particular, to semiconductor memory circuits capable of operating with low current and power consumption.
2. Description of the Related Art
Semiconductor memory circuits (e.g., dynamic random-access memory [DRAM] circuits, static random-access memory [SRAM] circuits, read-only memory [ROM], and programmable read-only memory [PROM] circuits) which can store and retrieve digital data (i.e., either a logic 1 or 0) are widely used in electronic devices. Such semiconductor memory circuits can be based on bipolar and/or metal-oxide-semiconductor (MOS) transistors.
FIG. 1 is an electrical schematic of a conventional NMOS semiconductor ROM circuit 10. NMOS semiconductor ROM circuit 10 includes a ROM memory core 12, a pre-charge circuit 14, and multiplexer (MUX) circuit 16 and a sense amplifier circuit 18.
The ROM memory core 12 includes a plurality (namely, m numbers) of bit lines (20a to 20m) and a plurality (namely, n numbers) of word lines (22a to 22n). The bit lines (a.k.a. physical columns) and word lines (a.k.a. physical rows) are arranged in an intersecting manner with NMOS transistors 24 at predetermined intersections thereof. The NMOS transistors 24 serve as memory cells of the ROM memory core 12. Since the memory cells (that is, NMOS transistors 24) are present only at predetermined intersections of the bit lines and word lines, ROM memory core 12 is known as a "ROM memory core with code."
The pre-charge circuit 14 includes a plurality of interconnected PMOS transistors 26. Each of the PMOS transistors 26 is electrically connected to one of the bit lines (20a to 20m) and to V.sub.DD (power supply voltage). The pre-charge circuit 14 is configured to pre-charge the bit lines (20a to 20m) to V.sub.DD prior to an operation of reading digital data from the memory core (i.e., prior to a "READ" operation).
The MUX circuit 16 includes a plurality of semiconductor device switches 28 and an output node 30. Each of the semiconductor device switches 28 is electrically connected to the pre-charge circuit 14 in a manner that provides for the MUX circuit 16 to select each of the bit lines (20a to 20m) as an input to the MUX circuit 16.
The sense amplifier circuit 18 is configured to sense the electrical state (e.g., the voltage state) of the output node 30 of the MUX circuit 16. The sense amplifier circuit 18 includes an input line 32 electrically connected to the output node 30 of the MUX circuit 16, an optional input reference line 34 and a sense amplifier circuit output line 36.
In conventional NMOS semiconductor ROM circuits, two types of conventional circuits are commonly employed as the sense amplifier circuit 18, namely a conventional differential amplifier circuit 40 (shown in FIG. 2) and a conventional inverter with a feedback pull-up circuit 60 (shown in FIG. 3). Conventional differential amplifier circuit 40 includes a plurality of interconnected MOS transistors 42. Conventional differential amplifier circuit 40 is configured to receive a reference signal, an input signal from the MUX circuit, and a control signal, as well as to provide an "out" signal in response (as illustrated in FIG. 2). The conventional inverter with a feedback pull-up circuit 60 is configured to receive an input signal, as well as to provide an "out" signal (as illustrated in FIG. 3).
Typically, during the operation of conventional semiconductor memory circuits, such as the NMOS semiconductor ROM circuit illustrated in FIG. 1, all bit lines are pre-charged to VDD by the pre-charge circuit prior to a READ operation. If the digital data to be read from a predetermined bit line is a digital 0, then the bit line will have been discharged to ground (i.e., a digital 0 or a "low" state) through a memory cell subsequent to its having been pre-charged. On the other hand, if the digital data to be read from the predetermined bit line is a digital 1, then the pre-charged bit line will be in a high impedance state (i.e., a digital 1 or a "high" state). The discharged to ground or high impedance state of the predetermined bit line is sensed and amplified by the sense amplifier circuit.
If, prior to the pre-charging of the bit lines, all the programmed digital data of the memory core are digital 0s, then the amount of current and power consumed during the pre-charging of the bit lines will be undesirably large. Furthermore, the greater the number of bit lines, the greater the consumption of current and power during a pre-charge operation. In a ROM core with a large number of bit lines and word lines, the power consumption required to pre-charge the bit lines can constitute the majority of the total power consumption of the semiconductor memory circuit. Further descriptions of conventional semiconductor memory circuits, their component circuits (e.g., ROM cores, pre-charge circuits and sense amplifier circuits) and their operation can be found in R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation, 260-263 and 331-354 (IEEE Press, 1997) and P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 269-353 (John Wiley & Sons, 1993), the disclosures of which are hereby fully incorporated by reference.
Still needed in the field, therefore, is a semiconductor memory circuit that provides for low current and power consumption during its operation. Also, it would be preferable for such a low power consumption semiconductor memory circuit to provide relatively high performance (i.e., speed).